ATMEGA640 Datasheet, PDF (82/407 Pages) ATMEL Corporation – 8- BIT Microcontroller with 256K Bytes In-System Programmable Flash

Note that enabling the alternate function of some of the port pins does not affect the use
of the other pins in the port as general digital I/O.
Ports as General Digital
I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 34 shows a
functional description of one I/O-port pin, here generically called Pxn.
Figure 34. General Digital I/O⁽¹⁾
QD
DDxn
Q _CLR
RESET
PUD
WDx
RDx
Configuring the Pin
Pxn
1
QD
PORTxn
0
Q _CLR
SLEEP
RESET
RRx
WRx
WPx
SYNCHRONIZER
DQ
LQ
DQ
PINxn
Q
RPx
clk _I/O
PUD:
SLEEP:
clk_I/O:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
clk_I/O, SLEEP, and PUD are common to all ports.
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
“Register Description for I/O-Ports” on page 112, the DDxn bits are accessed at the
DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at
the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written
logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-
ured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up
resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic
zero or the pin has to be configured as an output pin. The port pins are tri-stated when
reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is
driven high (one). If PORTxn is written logic zero when the pin is configured as an out-
put pin, the port pin is driven low (zero).
82 ATmega640/1280/1281/2560/2561
2549A–AVR–03/05