ATAM862-3 Datasheet, PDF (82/110 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

23.9.3
Serial Interface Status and Control Register (SISC)
Write
Read
Bit 3
MCL
---
Bit 2
RACK
TACK
Bit 1
SIM
ACT
Primary register address: "A"hex
Bit 0
IFN
SRDY
Reset value: 1111b
Reset value: xxxxb
MCL
RACK
TACK
SIM
IFN
SRDY
ACT
Multi-Chip Link activation
MCL = 1,multi-chip link disabled. This bit has to be set to "0" during
transactions to/from the internal EEPROM
MCL = 0, connects SC and SD additionally to the internal multi-chip link pads
Receive ACKnowledge status/control bit for MCL mode
RACK = 0, transmit acknowledge in next receive telegram
RACK = 1, transmit no acknowledge in last receive telegram
Transmit ACKnowledge status/control bit for MCL mode
TACK = 0, acknowledge received in last transmit telegram
TACK = 1, no acknowledge received in last transmit telegram
Serial Interrupt Mask
SIM = 1, disable interrupts
SIM = 0, enable serial interrupt. An interrupt is generated.
Interrupt FuNction
IFN = 1, the serial interrupt is generated at the end of telegram
IFN = 0, the serial interrupt is generated when the SRDY goes low (i.e., buffer
becomes empty/full in transmit/receive mode)
Serial interface buffer ReaDY status flag
SRDY = 1, in receive mode: receive buffer empty
in transmit mode: transmit buffer full
SRDY = 0, in receive mode: receive buffer full
in transmit mode: transmit buffer empty
Transmission ACTive status flag
ACT = 1, transmission is active, i.e., serial data transfer. Stop or start conditions
are currently in progress.
ACT = 0, transmission is inactive
23.9.4
Serial Transmit Buffer (STB) – Byte Write
First write cycle
Bit 3
Bit 2
Bit 1
Primary register address: "9"hex
Bit 0
Reset value: xxxxb
Second write cycle Bit 7 Bit 6 Bit 5 Bit 4
Reset value: xxxxb
The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift register and
starts shifting with the most significant bit.
82 ATAM862-3
4554E–4BMCU–05/06