ATV2500H Datasheet, PDF (8/15 Pages) ATMEL Corporation – High-Density UV-Erasable Programmable Logic Device

Preload and Observability of Registered Outputs
The ATV2500H/L's registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A V_IH level on the Odd I/O pins will force the
appropriate register high; a V_IL will force it low, independent
of the polarity or other configuration bit settings.
The preload state is entered by placing an 11V to 14V sig-
nal on pin 38 on the DIP and pin 42 on the SMP. When the
clock term is pulsed high, (pin 21 on the DIP, pin 23 on the
SMP) the data on the I/O pins is placed into the 12 regis-
ters chosen by the Q select and even/odd select pins.
Register 2 observability mode is entered by placing an 11V
to 14V signal on pin 2 (DIP or SMP). In this mode, the con-
tents of the buried register bank will appear on the associ-
ated outputs when the OE control signals are active.
Level forced on Odd
I/O pin during
preload cycle.
V_IH
V_IL
V_IH
V_IL
V_IH
V_IL
V_IH
V_IL
Q Select
pin state
Low
Low
High
High
Low
Low
High
High
Even/
Odd select
Low
Low
Low
Low
High
High
High
High
Even Q1 state
after cycle
High
Low
X
X
X
X
X
X
Even Q2 state
after cycle
X
X
High
Low
X
X
X
X
Odd Q1 state
after cycle
X
X
X
X
High
Low
X
X
Odd Q2 state
after cycle
X
X
X
X
X
X
High
Low
Power-Up Reset
The registers in the ATV2500H/L are designed to reset dur-
ing power-up. At a point delayed slightly from V_CC crossing
3.8V, all registers will be reset to the low state. The output
state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V_CC actually rises in the system, the fol-
lowing conditions are required:
1. The V_CC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock term
high,
3. The signals from which the clock is derived must
remain stable during t_PR.
Parameter Description Min Typ Max Units
t_PR
Power-Up
Reset Time
600 1000 ns
8
ATV2500H/L