ATA5278_06 Datasheet, PDF (8/34 Pages) ATMEL Corporation – Stand-alone Antenna Driver

3.6 SPI
The control interface of the ATA5278 consists of an eight-bit synchronous SPI. It has a clock
input (S_CLK) which supports frequencies up to 1 MHz, a chip select line (S_CS) which enables
the interface, a serial data input (S_DI) and a serial data output (S_DO). The output pin is of a
tristate type, which will be set to high-impedance state as soon as the chip-select line is dis-
abled. The interface is in slave mode configuration. This means that an SPI master (e.g. a
microcontroller) is required for communication with the ATA5278, as the IC will neither start a
communication by itself nor is it able to provide the serial clock signal. Figure 3-6 sketches the
internal structure.
Figure 3-6. SPI Structure
Internal data bus
8
S_CLK
MSB 6
5
4
3
2
1 LSB
Output register
S_DI
S_DO
MSB 6
5
4
3
2
1 LSB
Input register
tri
S_CS
8
Control logic/internal data bus
Once enabled by the chip-select line, the data at the S_DI pin is shifted into the input register
with every rising edge of the input clock signal. At the pin S_DO, the actual data of the LSB of
the output register is available. The output register is shifted on every falling edge of the input
clock signal. Two timing schemes for SPI data communication are supported, which are shown
in Figure 3-7 on page 9.
8 ATA5278
4832C–RKE–02/06