AT91R40008 Datasheet, PDF (8/18 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontroller

Product Overview
Power Supply
Input/Output
Considerations
Master Clock
Reset
NRST Pin
Watchdog Reset
Emulation Functions
Tri-state Mode
The AT91R40008 microcontroller has two types of power supply pins:
• VDDCORE pins, which power the chip core (i.e., the ARM7TDMI, embedded
memory and the peripherals).
• VDDIO pins, which power the I/O lines.
An independent I/O supply allows a flexible adaptation to external component signal
levels.
After the reset, the peripheral I/Os are initialized as inputs to provide the user with maxi-
mum flexibility. It is recommended that in any application phase, the inputs to the
AT91R40008 microcontroller be held at valid logic levels to minimize the power
consumption.
The AT91R40008 microcontroller has a fully static design and works on the Master
Clock (MCK) provided on the MCKI pin from an external source.
The Master Clock is also provided as an output of the device on the pin MCKO, which is
multiplexed through a general-purpose I/O line. While NRST is active, MCKO remains
low. After the reset, the MCKO is valid and outputs an image of the MCK signal. The
PIO controller must be programmed to use this pin as standard I/O line.
Reset restores the default states of the user interface registers (defined in the user inter-
face of each peripheral) and forces the ARM7TDMI to perform the next instruction fetch
from address zero. Except for the program counter, the ARM7TDMI registers do not
have defined reset states.
NRST is active low-level input. It is asserted asynchronously, but exit from reset is syn-
chronized internally to the MCK. The signal presented on MCKI must be active within
the specification for a minimum of 10 clock cycles up to the rising edge of NRST to
ensure correct operation.
The first processor fetch occurs 80 clock cycles after the rising edge of NRST.
The Watchdog can be programmed to generate an internal reset. In this case, the reset
has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not
sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted
and the Watchdog triggers the internal reset, the NRST pin has priority.
The AT91R40008 microcontroller provides a tri-state mode, which is used for debug
purposes. This enables the connection of an emulator probe to an application board
without having to desolder the device from the target board. In tri-state mode, all the out-
put pin drivers of the AT91R40008 microcontroller are disabled.
To enter tri-state mode, the NTRI pin must be held low during the last 10 clock cycles
before the rising edge of NRST. For normal operation, the NTRI pin must be held high
during reset by a resistor of up to 400 kΩ.
NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1.
Standard RS-232 drivers generally contain internal 400 kΩ pull-up resistors. If TXD1 is
connected to a device not including this pull-up, the user must make sure that a high
level is tied on NTRI while NRST is asserted.
8 _{AT91R40008 - Summary}
1732DS–ATARM–03/04