AT88SA10HS_10 Datasheet, PDF (8/23 Pages) ATMEL Corporation – Atmel CryptoAuthentication Host Security Chip

4.1.
IO Flags
The system is always the bus master, so before any IO transaction, the system must send an 8-bit flag to the chip
to indicate the IO operation that is to be performed, as follows:
Value
0x66
0x99
0xCC
Name
Command
Transmit
Sleep
Meaning
After this flag, the system starts sending a command block to the chip. The first bit of the block
can follow immediately after the last bit of the flag
After a turn-around delay, the chip will start transmitting the response for a previously transmitted
command block
Upon receipt of a sleep flag, the chip will enter a low power mode until the next Wake token is
received
All other values are reserved and will be ignored.
Note:
The values of flag for the Atmel AT88SA10HS host are different from that of the two clients, the Atmel AT88SA100S
and Atmel AT88SA102S. In this manner, both Atmel AT88SA102S (or Atmel AT88SA100S) and Atmel AT88SA10HS
can share the same communications pin on the system controller. While the AT88SA10HS will wake up when
communications are sent to the client, it will ignore all such transactions.
It is possible that data values transmitted to a client authentication chip (either the Atmel^® AT88SS100S or the
Atmel AT88SA102S) could be interpreted by the Atmel AT88SA10HS host chip as a legal Transmit flag. In this
case there could be a bus conflict as both the host and client chips drive the signal wire at the same time. To
prevent this, the PauseShort command should be used to prevent the AT88SA10HS host chip from looking at the
signal wire during any IO transaction to the client.
4.1.2. Command Timing
After a command flag is transmitted, a command block should be sent to the chip. During parsing of the
parameters and subsequent execution of a properly received command, the chip will be busy and not respond to
transitions on the signal pin. The delays for these operations are listed in the table below:
Table 4-2. Command Timing
Parameter
Symbol
Parsing Delay
t _PARSE
Host0Delay
Host1Delay
Host2Delay
MemoryDelay
SecureDelay
t _{EXEC_HOST0}
t _{EXEC_HOST1}
t _{EXEC_HOST2}
t _{EXEC_READ}
t _{EXEC_SECURE}
PersonalizeDelay t _PERSON
Max Unit Notes
100 μs Delay to check CRC and parse opcode and parameters before an error
indication will be available
13 ms Delay to execute any of the HOST0 command
7 ms Delay to execute any of the HOST1 command
0.5 ms Delay to execute any of the HOST2 command
3 ms Delay to execute Read command
36 ms Max delay to execute BurnSecure command at V_CC > 4.5V
See Section 5.6 for more details
13 ms Delay to execute GenPersonalizationKey
In this document, t_EXEC is used as shorthand for the delay corresponding to whatever command has been sent to
the chip.
8 Atmel AT88SA10HS Host Authentication Chip
8595F–SMEM–8/10