AT24C1024_05 Datasheet, PDF (8/18 Pages) ATMEL Corporation – Two-wire Serial EEPROM

Figure 5. Start and Stop Definition
Figure 6. Output Acknowledge
Device
Addressing
The 1024K EEPROM requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 7 on page 11). The device address
word consists of a mandatory one, zero sequence for the first five most significant bits as
shown. This is common to all two-wire EEPROM devices.
The 1024K uses the one device address bit, A1, to allow up to two devices on the same bus.
The A1 bit must compare to the corresponding hardwired input pin. The A1 pin uses an inter-
nal proprietary circuit that biases it to a logic low condition if the pin is allowed to float.
The seventh bit (P₀) of the device address is a memory page address bit. This memory page
address bit is the most significant bit of the data word address that follows. The eighth bit of
the device address is the read/write operation select bit. A read operation is initiated if this bit
is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the device will return to a standby state.
DATA SECURITY: The AT24C1024 has a hardware data protection scheme that allows the
user to write-protect the entire memory when the WP pin is at V_CC.
8 AT24C1024
1471N–SEEPR–12/05