ATMEGA16HVA_14 Datasheet, PDF (79/196 Pages) ATMEL Corporation – High Endurance Non-volatile Memorie segments

ATmega8HVA/16HVA
17.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
17-2 on page 79 shows a block diagram of the counter and its surroundings.
Figure 17-2. Counter Unit Block Diagram
DATA BUS
TCNTn
TOVn
(Int.Req.)
Clock Select
count _{Control Logic} ^clkTn
Edge
Detector
Tn
( From Prescaler )
top
Signal description (internal signals):
count
Increment or decrement TCNTn by 1.
clk_Tn
top
Timer/Counter clock, referred to as clk_Tn in the following.
Signalize that TCNTn has reached maximum value.
The counter is incremented at each timer clock (clk_Tn) until it passes its TOP value and then
restarts from BOTTOM. The counting sequence is determined by the setting of the WGMn0 bits
located in the Timer/Counter Control Register (TCCRnA). For more details about counting
sequences, see ”Timer/Counter Timing Diagrams” on page 85. clk_Tn can be generated from an
external or internal clock source, selected by the Clock Select bits (CSn2:0). When no clock
source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be
accessed by the CPU, regardless of whether clk_Tn is present or not. A CPU write overrides (has
priority over) all counter clear or count operations. The Timer/Counter Overflow Flag (TOVn) is
set when the counter reaches the maximum value and it can be used for generating a CPU
interrupt.
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8024A–AVR–04/08