AT83SND1C_06 Datasheet, PDF (78/212 Pages) ATMEL Corporation – Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface

Bit
Bit
Number Mnemonic Description
7-3
JUST4:0
Audio Stream Justification Bits
Refer to Section "Data Converter", page 74 for bits description.
DSEL Signal Output Polarity
2
POL Set to output the left channel on high level of DSEL output (PCM mode).
Clear to output the left channel on the low level of DSEL output (I²S mode).
Audio Data Size
1
DSIZ Set to select 32-bit data output format.
Clear to select 16-bit data output format.
High/Low Rate Bit
0
HLR Set by software when the PLL clock frequency is 384·Fs.
Clear by software when the PLL clock frequency is 256·Fs.
Reset Value = 0000 1000b
Table 75. AUDCON1 Register
AUDCON1 (S:9Bh) – Audio Interface Control Register 1
7
6
5
4
3
SRC
DRQEN MSREQ MUDRN
-
2
DUP1
1
DUP0
0
AUDEN
Bit
Number
7
6
5
4
3
Bit
Mnemonic Description
SRC
Audio Source Bit
Set to select C51 as audio source for voice or sound playing.
Clear to select the MP3 decoder output as audio source for song playing.
DRQEN
MP3 Decoded Data Request Enable Bit
Set to enable data request to the MP3 decoder and to start playing song.
Clear to disable data request to the MP3 decoder.
MSREQ
Audio Sample Request Flag Mask Bit
Set to prevent the SREQ flag from generating an audio interrupt.
Clear to allow the SREQ flag to generate an audio interrupt.
MUDRN
Audio Sample Under-run Flag Mask Bit
Set to prevent the UDRN flag from generating an audio interrupt.
Clear to allow the UDRN flag to generate an audio interrupt.
-
Reserved
The value read from this bit is always 0. Do not set this bit.
2-1
0
DUP1:0
AUDEN
Audio Duplication Factor
Refer to Table 73 for bits description.
Audio Interface Enable Bit
Set to enable the audio interface.
Clear to disable the audio interface.
Reset Value = 1011 0010b
Table 76. AUDSTA Register
AUDSTA (S:9Ch Read Only) – Audio Interface Status Register
7
6
5
4
3
2
1
0
SREQ
UDRN AUBUSY
-
-
-
-
-
78 AT8xC51SND1C
4109J–8051–10/06