AT89LP216_06 Datasheet, PDF (75/90 Pages) ATMEL Corporation – Microcontroller with 2K Bytes Flash

AT89LP216 [Preliminary]
23.8.6
Timing Parameters
The timing parameters for Figure 23-5, Figure 23-6, Figure 23-7, Figure 23-8, and Figure 23-10
are shown in Table .
Table 23-6. Programming Interface Timing Parameters
Symbol
Parameter
Min
t_CLCL
System Clock Cycle Time
t_PWRUP
Power On to SS High Time
t_POR
Power-on Reset Time
t_PWRDN
SS Tristate to Power Off
t_RLZ
RST Low to I/O Tristate
t_STL
RST Low Settling Time
t_RHZ
RST High to SS Tristate
t_SCK
Serial Clock Cycle Time
t_SHSL
Clock High Time
t_SLSH
Clock Low Time
t_SR
Rise Time
t_SF
Fall Time
t_SIS
Serial Input Setup Time
t_SIH
Serial Input Hold Time
t_SOH
Serial Output Hold Time
t_SOV
Serial Output Valid Time
t_SOE
Output Enable Time
t_SOX
Output Disable Time
t_SSE
SS Enable Lead Time
t_SSD
SS Disable Lag Time
t_ZSS
SCK Setup to SS Low
t_SSZ
SCK Hold after SS High
t_WR
Write Cycle Time
t_AWR
Write Cycle with Auto-Erase Time
t_ERS
Chip Erase Cycle Time
Note: 1. t_SCK is independent of t_CLCL.
0
10
t_CLCL
100
0
200⁽¹⁾
75
50
10
10
t_SLSH
t_SLSH
25
25
2.5
5
7.5
Max
60
100
1
2 t_CLCL
2 t_CLCL
25
25
10
35
10
25
Units
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
75
3621A–MICRO–6/06