ATTINY13_08 Datasheet, PDF (70/176 Pages) ATMEL Corporation – 8-bit Microcontroller with 1K Bytes In-System Programmable Flash

Table 11-3. Compare Output Mode, Fast PWM Mode⁽¹⁾
COM01
0
COM00
0
Description
Normal port operation, OC0A disconnected.
0
1
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
1
0
Clear OC0A on Compare Match, set OC0A at TOP
1
1
Set OC0A on Compare Match, clear OC0A at TOP
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 64
for more details.
Table 11-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-
rect PWM mode.
Table 11-4. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾
COM0A1
0
0
COM0A0
0
1
Description
Normal port operation, OC0A disconnected.
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
1
0
Clear OC0A on Compare Match when up-counting. Set OC0A on
Compare Match when down-counting.
1
1
Set OC0A on Compare Match when up-counting. Clear OC0A on
Compare Match when down-counting.
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 66 for more details.
• Bits 5:4 – COM0B1:0: Compare Match Output B Mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0
bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin
must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the
WGM02:0 bit setting.
Table 11-5 on page 71 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to
a normal or CTC mode (non-PWM).
70 ATtiny13
2535I–AVR–05/08