U2730B-N Datasheet, PDF (7/17 Pages) ATMEL Corporation – L-band Down-converter for DAB Receivers

U2730B-N
Reference Divider
Nine different scaling factors of the reference divider can be selected by different volt-
age settings at the input pins SI1, SI2: 32, 33⁽¹⁾, 35, 36, 48, 49⁽¹⁾, 65⁽¹⁾, 64, 63⁽¹⁾. The
reference divider factors result in reference oscillator frequencies shown in Table 1.
Note:
1. These scaling factors result in an output frequency of the reference divider of
512 kHz. If harmonics of the Bd. 3 VCO are falling in the L-band reception band, this
spurious can influence the AGC of U2730B-N. That could be a problem for small
incoming signals. In this case it is possible to switch the reference divider from nref to
nref+1.
LO Divider
The LO divider is operated at the fixed division ratio 2464. Assuming the settings
described in the section “Reference Divider”, the oscillator's frequency is controlled to
be 1261.568 MHz in locked state and the output frequency of the RF divider is 512 kHz.
Phase Comparator,
Charge Pump and Loop
Filter
The tri-state phase detector causes the charge pump to source or to sink current at the
output pin PD depending on the phase relation of its input signals which are provided by
the reference and the RF divider respectively. By means of the control pin CI, two differ-
ent values of this current can be selected, and furthermore the charge-pump current can
be switched off.
The input of the high-gain amplifier (output pin CD) which is implemented in order to
construct a loop filter, as shown in the application circuit, can be switched to GND by
means of the control pin CI (see Table 2). In the application circuit, the loop filter is com-
pleted by connecting the pins PD and CD by an appropriate RC network.
Lock Detector
An internal lock detector checks if the phase difference of the input signals of the phase
detector is smaller than approximately 250 ns in seven subsequent comparisons. If a
phase lock is detected, the open collector output pin PLCK is set to HIGH. It should be
noted that the output current of this pin must be limited by external circuitry as it is not
limited internally. If the voltage at the control pin CI is chosen to be half the supply volt-
age, or if this control pin is left open, the lock-detector function is deactivated and the
logical value of the PLCK output is undefined.
Test Interface
If the input control pin CI is left open (high impedance state), a test signal which moni-
tors the output frequency of the reference divider appears at the output pin TI.
In analogy to the reference divider a test signal which monitors the output frequency of
the RF divider appears at the test interface output pin TI if the input control pin CI is con-
nected to VCC/2.
Table 2. Control Interface (CI) Settings
CI
PD
GND
200 µA
Vs
300 µA
VCC/2
0 µA
Open
Connected to GND
PLCK
ok
ok
Undefined
Undefined
TI
–
–
RF divider
Reference divider
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4719A–DAB–05/03