AT7909E_14 Datasheet, PDF (7/20 Pages) ATMEL Corporation – System-on-chip technology to handle all ground link communication

AT7909E
6. Signal pins description
The AT7909E inputs and outputs are as defined in the tables below. For each signal, the type is
indicated (CMOS, Schmitt). For each output signal, the drive strength is indicated (LD/MD/HD =
Low/Mid/High Drive). PD stands for Pull-Down, and PDL stands for Pull-Down Low resistance.
Clock in the rightmost column is the name of the reference clock if the signal is synchronous.
6.1 General AT7909E signals
Table 6-1. Internal Scan Control Interface Signals
Signal
TestSE
TestMode
TestSignalIn[1:6]
TestSignalOut[1:5]
Type
I, CMOS, PD
I, CMOS, PD
I, CMOS
O, CMOS, LD
Description
Reserved for manufacturing
test. Shall be tied to GND.
Reserved for manufacturing
test. Shall be tied to GND.
Reserved for manufacturing
test. Shall be tied to GND.
Reserved for manufacturing
test.
Clock
strap
strap
strap
open
Signal
JtagTck
JtagTdi
JtagTms
JtagTRstN
JtagTdo
Table 6-2. Test Access Port interface signals
Type
I, CMOS, PD
I, CMOS, PD
I, CMOS, PD
I, CMOS, PD
O, CMOS, LD
Description
JTAG TAP Test Clock
JTAG TAP Test Data In
JTAG TAP Test Mode Select
JTAG TAP Test Reset
JTAG TAP Test Data Out
Clock
-
JtagTck
JtagTck
JtagTck
JtagTck
Signal
SysClk
SpwClk
TmClk1
TmClk2
PoResetN
Table 6-3. Clocks and Reset interface signals
Type
I, CMOS
I, CMOS
I, CMOS
I, CMOS
I, Schmitt
Description
Clock
The main source clock. Can be configured to be
-
the source clock for the SpwClk and TmClk as
well.
May be connected inside the AT7909E to the
-
internal SpwClk
May be connected inside the AT7909E to the
-
TmClk
May be connected inside the AT7909E to the
-
TmClk
Power On Reset. (Full reset)
-
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7693A–AERO–06/07