AT73C500 Datasheet, PDF (7/28 Pages) ATMEL Corporation – Chip Set Solution for Watt-Hour Meters

AT73C500
If the nominal voltage is chosen to be 120V, the voltage
divider can either have the same configuration as in the
230V meter, or it can be modified to produce 2.0V_pp with
140V phase voltage. In the latter case, the default meter
constant will be roughly twice the constant of 230V meter,
i.e. 2411 impulses/kWh. The meter constant can be scaled
to an even number value by means of calibration.
As described above, the configuration of voltage dividers
and current transformers affects to almost all parameters
being metered, like energy counters and impulse outputs.
A calibration coefficient is provided for the adjustment of
the display pulse rates. With this coefficient, the effect of
various voltage divider and current transformer configura-
tions can be compensated. Care should be taken that the
dynamic range of the A/D converters is always effectively
utilized. The use of calibration coefficients is described in
the next section.
Current and voltage samples of AT73C501/AT73C502 are
multiplexed and transferred to AT73C500 through a serial
interface. The timing of the interface is presented in the
next section.
AT73C501/AT73C502 contain an internal bandgap voltage
reference. When used in class 0.5 and 0.2 meters, smaller
temperature drift is required. This can be achieved by
bypassing the internal reference and using temperature
compensated external reference instead. The reference is
selected with the BGD input.
BGD
0 (V_SS)
1 (V_DD)
Reference
Internal
External
There is an integrated voltage monitoring block on the con-
verter chip. The PFAIL output is forced high if the level of
voltage supplied to V_CIN input drops below 4.2V. There is a
hysteresis in the monitoring function and PFAIL returns low
if voltage at V_CIN is raised back above 4.3V.
PFAIL output of AT73C501/AT73C502 can be connected
to an interrupt input of AT73C500. AT73C500 detects the
rising edge of PFAIL. To assure reliable power-down pro-
cedure after voltage break, the V_CC supply of AT73C500
must be equipped with a 470 µF or larger capacitor.
AT73C500
AT73C500 performs power and energy calculations. It also
controls the interfacing to the AT73C501 (or AT73C502)
and to an external microprocessor. The block diagram of
the DSP is presented below.
Figure 7. Block diagram of DSP software
u1(n)
u2(n)
u3(n)
i1(n)
i2(n)
i3(n)
DC OFFSET
SUPPRESSION
FREQUENCY
MEASUREMENT
VOLTAGE
MEASUREMENT
PHASE
CALIBRATION
ACTIVE POWER
MEASUREMENT
HILBERT
TRANSFORM
REACTIVE POWER
MEASUREMENT
GAIN
CALIBRATION
GAIN AND OFFSET
CALIBRATION
GAIN AND OFFSET
CALIBRATION
f
CURRENT
DERIVATION
I
U
ACTIVE ENERGY
CALCULATION
W
P
APPARENT POWER
EVALUATION
POWER FACTOR
DERIVATION
PF
Q
REACTIVE ENERGY
CALCULATION
Wq
Serial Bus Interface
The timing of the serial bus interface connecting the ADC
and DSP devices is presented in Figure 5. The same bus is
used to read the calibration data from an external
EEPROM. This operation is described in section “Loading
of Calibration Coefficients” on page 19.
When the three current and three voltage samples are
ready, AT73C501/AT73C502 raises the ACK output.
AT73C500 detects the rising edge of ACK, and, after a few
clock cycles, it is ready to read the samples through the
serial bus. The transfer is initiated by CS/SOUT1 signal
and the data bits are strobed in at the falling edge of
CLKR/SCLK clock. Six 16-bit samples is transferred in the
following sequence: I1, U1, I2, U2, I3 and U3.
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