AT24C02B_07 Datasheet, PDF (7/21 Pages) ATMEL Corporation – Two-wire Serial EEPROM

Bus Timing
Figure 2. SCL: Serial Clock, SDA: Serial Data I/O^®
AT24C02B
Write Cycle Timing
Figure 3. SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
WORDn
ACK
STOP
CONDITION
twr⁽¹⁾
START
CONDITION
Note: 1. The write cycle time t_WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
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5126F–SEEPR–2/07