90E32A_14 Datasheet, PDF (65/71 Pages) ATMEL Corporation – Poly-Phase High-Performance

90E32A
POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
7.3
INTERFACE TIMING
7.3.1
SPI INTERFACE TIMING (SLAVE MODE)
The SPI interface timing is as shown in Figure-17 and Table-16.
CS
SCLK
SDI
SDO
t_CSS
t_CYC
t_CLH
t_CLL
t_DIS t_DIH
Valid Input
t_DW
High Impedance
t_PD
Valid Output
t_CSH
t_CSD
t_CLD
t_DF
High Impedance
Figure-17 SPI Timing Diagram
Table-16 SPI Timing Specification
Symbol
Description
t_CSH
Minimum CS High Level Time
t_CSS
CS Setup Time
t_CSD
CS Hold Time
t_CLD
Clock Disable Time
t_CYC
SCLK cycle
t_CLH
t_CLL
t_DIS
t_DIH
t_DW
t_PD
t_DF
Note:
Clock High Level Time
Clock Low Level Time
Data Setup Time
Data Hold Time
Minimum Data Width
Output Delay
Output Disable Time
1. T means system clock cycle. T=1/f_{sys_clk}
Min.
2T ^{note 1}+10
2T+10
3T+10
1T
7T+10
5T+10
2T+10
2T+10
1T+10
3T+10
Typical
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2T+20
ns
2T+20
ns
Electrical Specification
65
April 2, 2013