T48C862-R3 Datasheet, PDF (64/107 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

T3CS1 Timer 3 Clock Source select bit 1 T3CS1 TCS0 Counter 3 Input Signal (CL3)
T3CS0 Timer 3 Clock Source select bit 0 1
1 System clock (SYSCL)
1
0 Output signal of Timer 2 (POUT)
0
1 Output signal of Timer 1 (T1OUT)
0
0 External input signal from T3I edge
detect
Timer 3 Compare- and
Compare-mode Register
Timer 3 Compare-Mode
Register 1 (T3CM1)
Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of
Timer 3. The timer compares the content of the compare register with the current
counter value. If both match, it generates a signal. This signal can be used for the
counter reset, to generate a timer interrupt, for toggling the output flip-flop, as SSI clock
or as clock for the next counter stage. For each compare register, a compare-mode reg-
ister exists. These registers contain mask bits to enable or disable the generation of an
interrupt, a counter reset, or an output toggling with the occurrence of a compare match
of the corresponding compare register. The mask bits for activating the single-action
mode can also be located in the compare mode registers. When assigned to the com-
pare register a compare event will be suppressed.
Address: "B"hex - Subaddress: "2"hex
T3CM1
Bit 3
T3SM1
Bit 2
T3TM1
Bit 1
T3RM1
Bit 0
T3IM1
Reset value: 0000b
T3SM1
Timer 3 Single action Mask bit 1
T3SM1 = 0, disables single-action compare mode
T3SM1 = 1, enables single-compare mode. After this bit is set, the compare
register (T3CO1) is used until the next compare match.
T3TM1
Timer 3 compare Toggle action Mask bit 1
T3TM1 = 0, disables compare toggle
T3TM1 = 1, enables compare toggle. A match of Counter 3 with the compare
register (T3CO1) toggles the output flip-flop (TOG3).
T3RM1
Timer 3 Reset Mask bit 1
T3RM1 = 0, disables counter reset
T3RM1 = 1, enables counter reset. A match of Counter 3 with the compare
register (T3CO1) resets the Counter 3.
T3IM1
Timer 3 Interrupt Mask bit 1
T3RM1 = 0, disables Timer 3 interrupt for T3CO1 register.
T3RM1 = 1, enables Timer 3 interrupt for T3CO1 register.
T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1
64 T48C862-R3
4554A–4BMCU–02/03