AT91SAM9G20_1 Datasheet, PDF (628/832 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

After transmission, the control bits are written back to the second word of the first buffer along
with the “used” bit and other status information. Bit 31 is the “used” bit which must be zero when
the control word is read if transmission is to happen. It is written to one when a frame has been
transmitted. Bits 27, 28 and 29 indicate various transmit error conditions. Bit 30 is the “wrap” bit
which can be set for any buffer within a frame. If no wrap bit is encountered after 1024 descrip-
tors, the queue pointer rolls over to the start in a similar fashion to the receive queue.
The transmit buffer queue pointer register must not be written while transmit is active. If a new
value is written to the transmit buffer queue pointer register, the queue pointer resets itself to
point to the beginning of the new queue. If transmit is disabled by writing to bit 3 of the network
control, the transmit buffer queue pointer register resets to point to the beginning of the transmit
queue. Note that disabling receive does not have the same effect on the receive queue pointer.
Once the transmit queue is initialized, transmit is activated by writing to bit 9, the Transmit Start
bit of the network control register. Transmit is halted when a buffer descriptor with its used bit set
is read, or if a transmit error occurs, or by writing to the transmit halt bit of the network control
register. (Transmission is suspended if a pause frame is received while the pause enable bit is
set in the network configuration register.) Rewriting the start bit while transmission is active is
allowed.
Transmission control is implemented with a Tx_go variable which is readable in the transmit sta-
tus register at bit location 3. The Tx_go variable is reset when:
– transmit is disabled
– a buffer descriptor with its ownership bit set is read
– a new value is written to the transmit buffer queue pointer register
– bit 10, tx_halt, of the network control register is written
– there is a transmit error such as too many retries or a transmit underrun.
To set tx_go, write to bit 9, tx_start, of the network control register. Transmit halt does not take
effect until any ongoing transmit finishes. If a collision occurs during transmission of a multi-
buffer frame, transmission automatically restarts from the first buffer of the frame. If a “used” bit
is read midway through transmission of a multi-buffer frame, this is treated as a transmit error.
Transmission stops, tx_er is asserted and the FCS is bad.
If transmission stops due to a transmit error, the transmit queue pointer resets to point to the
beginning of the transmit queue. Software needs to re-initialize the transmit queue after a trans-
mit error.
If transmission stops due to a “used” bit being read at the start of the frame, the transmission
queue pointer is not reset and transmit starts from the same transmit buffer descriptor when the
transmit start bit is written
Table 36-2. Transmit Buffer Descriptor Entry
Bit
31:0 Byte Address of buffer
Function
Word 0
Word 1
628 AT91SAM9G20 Preliminary
6384D–ATARM–04-May-09