AVR32AP Datasheet, PDF (60/181 Pages) ATMEL Corporation – 32-bit AVR Microcontroller

The translation process performed by PerformPagedAccess( ) can be described as as shown in
Table 4-9.
Table 4-9. PerformPagedAccess( ) pseudo-code example
match ← 0;
for (i=0; i<TLBentries; i++)
if ( Compare(TLB[i]_VPN, VA, TLB[i]_SZ, TLB[i]_V) )
// VPN and VA matches for the given page size and entry valid
if ( SharedVirtualMemoryMode or
(PrivateVirtualMemoryMode and ( TLB[i]_G or (TLB[i]_ASID==TLBEHI_ASID) ) ) )
if (match == 1)
SignalException(TLBmultipleHit);
else
match ← 1;
TLB[i]_A ← 1;
ptr ← i;
// pointer points to the matching TLB entry
endif;
endif;
endfor;
if (match == 0 )
SignalException(ITLBmiss);
endif;
if (InApplicationMode)
if (TLB[ptr]_AP[2] == 0)
SignalException(ITLBprotection);
endif;
endif;
if (TLB[ptr]_AP[0] == 0)
SignalException(ITLBprotection);
endif;
if (TLB[ptr]_C == 1)
PerformAccess(cached);
else
PerformAccess(non-cached);
endif;
4.3 Operation of the MMU and MMU exceptions
The MMU uses both hardware and software mechanisms in order to perform its memory remap-
ping operations. The following tasks are performed by hardware:
1. The MMU decodes the virtual address and tries to find a matching entry in the TLB.
This entry is used to generate a physical address. If no matching entry is found, a TLB
miss exception is issued.
2. The matching entry is used to determine whether the access has the appropriate
access rights, cacheability, bufferability and so on. If the access is not permitted, a TLB
Protection Violation exception is issued.
60 AVR32
32001A–AVR32–06/06