ATMEGA162 Datasheet, PDF (60/323 Pages) ATMEL Corporation – 8-Bit AVR Microcontroller with 16K Bytes In-System ProgrammableFlash

Moving Interrupts Between
Application and Boot Space
General Interrupt Control
Register – GICR
When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes and the
IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical
and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code
Comments
.org 0x1C00
0x1C00
0x1C02
jmp RESET
jmp EXT_INT0
; Reset handler
; IRQ0 Handler
0x1C04
jmp EXT_INT1
; IRQ1 Handler
...
....
..
;
0x1C36
jmp SPM_RDY
; Store Program Memory Ready Handler
;
0x1C38 RESET: ldi r16,high(RAMEND) ; Main program start
0x1C39
out SPH,r16
; Set Stack Pointer to top of RAM
0x1C3A
ldi r16,low(RAMEND)
0x1C3B
out SPL,r16
0x1C3C
sei
; Enable interrupts
0x1C3D
<instr> xxx
The General Interrupt Control Register controls the placement of the Interrupt Vector
table.
Bit
7
6
5
4
3
2
1
0
INT1
INT0
INT2
PCIE1 PCIE0
–
IVSEL
IVCE
GICR
Read/Write
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the
Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the begin-
ning of the Boot Loader section of the Flash. The actual address of the start of the Boot
Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader
Support – Read-While-Write Self-programming” on page 216 for details. To avoid unin-
tentional changes of Interrupt Vector tables, a special write procedure must be followed
to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are
disabled in the cycle IVCE is set, and they remain disabled until after the instruction fol-
lowing the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four
cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note:
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-
grammed, interrupts are disabled while executing from the Application section. If
Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro-
gramed, interrupts are disabled while executing from the Boot Loader section. Refer to
the section “Boot Loader Support – Read-While-Write Self-programming” on page 216
for details on Boot Lock bits.
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is
cleared by hardware four cycles after it is written or when IVSEL is written. Setting the
60 ATmega162/V
2513F–AVR–12/03