U3600BM_05 Datasheet, PDF (6/44 Pages) ATMEL Corporation – Single-chip Cordless Telephone IC

3.3 Speed-up of the Loop Filter of PLL1 (“Modulator PLL”)
To have a fast locking time for the modulator loop there is a precharge and a speed-up mode for
the external loop filter.
During receive mode (VCO3 enabled, VCO1 disabled) the modulator loop filter is precharged to
about half of the internally regulated 2.5V charge-pump voltage.
During the first 30 ms after enabling VCO1 the modulator phase comparator is in speed-up
mode. In this mode the current of the pase comparator which charges the loop filter is much
larger than in normal mode. Additionally to the automatically switched 30 ms speed-up mode,
the speed-up can be activated for any time by setting the bit SU1.
3.4 Speed-up of the Loop Filter of PLL3 (“1st. LO.”)
Similiar to PLL1, there is also a possibility to increase the locking speed of PLL3. This can be
done by setting the bit SU3. Having done this, the charge pump at the output of the phase com-
parator has a bigger current capability and therefore charges the external capacitors faster.
3.5 Adjustment of the Modulator Gain
To fulfil the different requirements of the different countries three conversion gains of the modu-
lator are selectable by the bits GMOD [1:0] (R6: D2, D3).
Country settings see tables at channel frequencies and dividers. Ranges see electrical charac-
teristics at RF transmitter.
3.6 Modulator PLL
The fractional divider has been chosen to increase the reference frequency of the modulator
PLL.
557.5 kHz = f_Mod/ _⎝⎛P₁ + ₂--^Q--₂---¹₃--_⎠⎞
P₁: integer part of the fractional divider (M = 1)
Q₁: fractional part of the fractional divider (M = 1)
Q₁
=
223 ×
⎛
⎝
--------^f--^M----^o---^d---------
557.5 kHz
–
P_{1⎠⎞}
223 = ⁵----⁵---⁷----^.-⁵-----^k---^H-----^z-
2.5 kHz
The frequency step 2.5 kHz is a fraction of the reference frequency 557.5 kHz.
In fact, the fractional divider divides Q₁ times by (P₁ + 1) and (223 – Q₁) times by P₁
during 223 cycles.
→^Q-----¹-----^×-----⁽---^P----¹----+-----¹----₂⁾---₂^+---₃--⁽---²---²---³-----–-----^Q-----¹---⁾--^P----¹-
=
P₁
+
--^Q-----¹--
223
For each comparison cycle (f_Ref1 = 557.5 kHz), the accumulator content is incremented by the
Q₁ value and the divider divides by the P₁ value. When the accumulator value reaches or
exceeds 223, the divider divides by the value (P₁ + 1). Then, the accumulator holds the excess
value (accumulator value - 223). After 223 cycles, the correct division is executed.
6 U3600BM
4516D–CT0–10/05