MG2RT Datasheet, PDF (6/13 Pages) ATMEL Corporation – Rad Tolerant 350K Used Gates 0.5 μm CMOS Sea of Gates

Design Flows and Tools
Design Flows and
Modes
A generic design flow for an MG2RT array is illustrated below.
A top down design methodology is proposed which starts with high level system description and
is refined in successive design steps. At each step, structural verification is performed which
includes the following tasks:
• Gate level logic simulation and comparison with high level simulation results.
• Design and test rules check.
• Power consumption analysis.
• Timing analysis (only after floor plan).
The main design stages are:
• System specification, preferably in VHDL form.
• Functional description at RTL level.
• Logic synthesis.
• Floor planning and bonding diagram generation.
• Test/Scan insertion, ATG and/or fault simulation.
• Physical cell placement, JTAG insertion and clock tree synthesis.
• Routing.
To meet the various requirements of designers, several interface levels between the customer
and Atmel are possible.
For each of the possible design modes a review meeting is required for data transfer from the
user to Atmel. In all cases the final routing and verifications are performed by Atmel.
The design acceptance is formalized by a design review which authorizes Atmel to proceed with
sample manufacturing.
6 MG2RT
4115L–AERO–06/05