AT89LP52_14 Datasheet, PDF (6/117 Pages) ATMEL Corporation – 8-bit Microcontroller Compatible with 8051 Products

2. Overview
The AT89LP51/52 is a low-power, high-performance CMOS 8-bit microcontroller with 4K/8K
bytes of In-System Programmable Flash program memory and 256 bytes of Flash data memory.
The device is manufactured using Atmel's high-density nonvolatile memory technology and is
compatible with the industry-standard 80C52 instruction set.
The AT89LP51/52 is built around an enhanced CPU core that can fetch a single byte from mem-
ory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing
instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP51/52 CPU, instructions need
only 1 to 4 clock cycles providing 6 to 12 times more throughput than the standard 8051. Sev-
enty percent of instructions need only as many clock cycles as they have bytes to execute, and
most of the remaining instructions require only one additional clock. The enhanced CPU core is
capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the
same current consumption. Conversely, at the same throughput as the classic 8051, the new
CPU core runs at a much lower speed and thereby greatly reducing power consumption and
EMI. The AT89LP51/52 also includes a compatibility mode that will enable classic 12 clock per
machine cycle operation for true timing compatibility with AT89S51/52.
The AT89LP51/52 provides the following standard features: 4K/8K bytes of In-System
Programmable Flash program memory, 256 bytes of Flash data memory, 256 bytes of RAM, up
to 36 I/O lines, three 16-bit timer/counters, a programmable watchdog timer, a full-duplex serial
port, an on-chip crystal oscillator, an internal 1.8432 MHz auxiliary oscillator, and a four-level,
six-vector interrupt system. A block diagram is shown in Figure 2-1.
Key Benefits:
• Full software and timing compatibility with AT89S52 means no changes to existing software,
including fetching from external ROM or read/write from/to external RAM
• Disable compatibility mode to achieve on average 9 times more throughput at the same
current consumption and frequency as AT89S52; or lower the clock frequency 9 times and
achieve the same speed as AT89S52 but with more than 5 times less current consumption
• Save even more power and the cost of a quartz crystal by using the internal 1.8432 MHz RC
oscillator, which is Vcc and temperature compensated well enough to ensure proper UART
serial communications. Together with the built-in POR and the BOD circuits, you do not need
any external components for AT89LP52 to provide the reset and clock functions
• All three timer/counters of the AT89LP51/52, Timer 0, Timer 1 and Timer 2, can be
configured to toggle a port pin on overflow for clock/waveform generation. Unlike AT89S51,
Timer 2 is also present on AT89LP51
• The enhanced full-duplex UART of the AT89LP51/52 includes Framing Error Detection and
Automatic Address Recognition. In addition, enhancements to Mode 0 allow hardware
accelerated emulation of a master SPI or TWI
• Use In-Application Programming to alter the built-in 8K Flash program memory while
executing the application, in effect making it possible to have programmable data tables
embedded in the program code. Or use the 256-byte Flash Data memory for nonvolatile data
storage
• Each 8-bit I/O port of the AT89LP51/52 can be independently configured in one of four
operating modes. In quasi-bidirectional mode, the port operates as in the classic 8051. In
input-only mode, the port is tristated. Push-pull output mode provides full CMOS drivers and
open-drain mode provides just a pull-down. Unlike other 8051s, this allows Port 0 to operate
with on-chip pull-ups if desired
6 AT89LP51/52
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