AT88SA10HS Datasheet, PDF (6/23 Pages) ATMEL Corporation – CryptoAuthentication™ Host Security Chip

Table 3. AC Parameters
Parameter
Wake Low
Duration
Wake Delay to
Data Comm.
Start pulse
duration
Symbol
t _WLO
t _WHI
t _START
Direction
To
CryptoAuthentication
To
CryptoAuthentication
To
CryptoAuthentication
From
CryptoAuthentication
Min Typ Max Unit
Notes
60
- μs Signal can be stable in either high or low
levels during extended sleep intervals.
1
- ms Signal should be stable high for this
entire duration.
4.1 4.34 4.56 μs
4.62 6.0 8.6 μs
Zero
t _ZHI
transmission
high pulse
Zero
transmission
low pulse
Bit time^‡
t _ZLO
t _BIT
To
CryptoAuthentication
From
CryptoAuthentication
To
CryptoAuthentication
From
CryptoAuthentication
To
CryptoAuthentication
Turn around
delay
t
TURNAROUND
From
CryptoAuthentication
From
CryptoAuthentication
To
CryptoAuthentication
High side
glitch filter @
active
Low side glitch
filter @ active
t _{HIGNORE_A}
t _{LIGNORE_A}
To
CryptoAuthentication
To
CryptoAuthentication
High side
glitch filter @
sleep
Low side glitch
filter @ sleep
IO Timeout
t _{HIGNORE_S}
t _{LIGNORE_S}
t _TIMEOUT
To
CryptoAuthentication
To
CryptoAuthentication
To
CryptoAuthentication
Watchdog
reset
Pause Length
t _WATCHDOG ^To
CryptoAuthentication
t _PAUSE
-
4.1 4.34 4.56 μs
4.62 6.0 8.6 μs
4.1 4.34 4.56 μs
4.62 6.0 8.6 μs
37.1 39 - μs If the bit time exceeds t _TIMEOUT then
CryptoAuthentication will enter sleep
mode and the wake token must be
resent.
46.2 60 86 μs
46.2 60 86 μs CryptoAuthentication will initiate the first
low going transition after this time interval
following the end of the Transmit flag
46.2 60 86 μs After CryptoAuthentication transmits the
last bit of a block, system must wait this
interval before sending the first bit of a
flag
45
ns Pulses shorter than this in width will be
ignored by the chip, regardless of its
state when active
45
ns Pulses shorter than this in width will be
ignored by the chip, regardless of its
state when active
2
μs Pulses shorter than this in width will be
ignored by the chip when in sleep mode
2
μs Pulses shorter than this in width will be
ignored by the chip when in sleep mode
7 10 13 ms Starting as soon as 7ms up to 13ms
after the initial signal transition of a token
the chip will enter sleep if no complete &
valid token is received.
3 4 5.2 s Max. time from wake until chip is forced
into sleep mode. Refer to Section 3.5
18
25
32
ms
Duration during which the chip will ignore IO
on the bus. See PauseShort command.
‡ START, ZLO, ZHI & BIT are designed to be compatible with a standard UART running at 230.4K baud for both
transmit and receive.
6 AT88SA10HS Host Authentication Chip [Preliminary]
8595B–SMEM–09/09