AT75C140 Datasheet, PDF (6/18 Pages) ATMEL Corporation – Smart Internet Appliance Processor (SIAP-TM)

Table 3. AT75C140 Pin Description List in 208-lead PQFP Package and 256-ball PBGA Package (Continued)
Block
Pin Name in Package Type
256-ball PBGA 208-lead PQFP
Function
Active
Level
Type
MAC A Interface
MA_COL
MA_COL
MAC A Collision Detect
-
Input
MA_CRS
MA_CRS
MAC A Carrier Sense
-
Input
MA_TXER
MA_TXER
MAC A Transmit Error
-
Output, TS
MA_TXD[3:0]
MA_TXD[3:0]
MAC A Transmit Data Bus
-
Output, TS
MA_TXEN
MA_TXEN
MAC A Transmit Enable
-
Output, TS
MA_TXCLK
MA_TXCLK
MAC A Transmit Clock
-
Input
MA_RXD[3:0]
MA_RXD[3:0] MAC A Receive Data Bus
-
Input
MA_RXER
MA_RXER
MAC A Receive Error
-
Input
MA_RXCLK
MA_RXCLK
MAC A Receive Clock
-
Input
MA_RXDV
MA_RXDV
MAC A Receive Data Valid
-
Input
MA_MDC
MA_MDC
MAC A Management Data Clock
-
Output, TS
MA_MDIO
MA_MDIO
MAC A Management Data Bus
-
I/O, PD
MA_LINK
MA_LINK
MAC A Link Interrupt
-
Input
MAC B Interface
MB_COL
MB_COL
MAC B Collision Detect
-
Input
MB_CRS
MB_CRS
MAC B Carrier Sense
-
Input
MB_TXER
MB_TXER
MAC B Transmit Error
-
Output, TS
MB_TXD[3:0]
MB_TXD[3:0]
MAC B Transmit Data Bus
-
Output, TS
MB_TXEN
MB_TXEN
MAC B Transmit Enable
-
Output, TS
MB_TXCLK
MB_TXCLK
MAC B Transmit Clock
-
Input
MB_RXD[3:0]
MB_RXD[3:0] MAC B Receive Data Bus
-
Input
MB_RXER
MB_RXER
MAC B Receive Error
-
Input
MB_RXCLK
MB_RXCLK
MAC B Receive Clock
-
Input
MB_RXDV
MB_RXDV
MAC B Receive Data Valid
-
Input
MB_MDC
MB_MDC
MAC B Management Data Clock
-
Output, TS
MB_MDIO
MB_MDIO
MAC B Management Data Bus
-
I/O, PD
MB_LINK
MB_LINK
MAC B Link Interrupt
-
Input
Power
GND
GND
Ground
-
Ground
PLL_GND
PLL_GND
PLL Ground
-
Ground
PLL_VDD
PLL_VDD
PLL Power
-
Power
VDD2V5
VDD2V5
2.5V Nominal Supply
-
Power
VDD3V3
VDD3V3
3.3V Nominal Supply
-
Power
6 AT75C140
2659A–INTAP–09/02