AT25320B_14 Datasheet, PDF (6/24 Pages) ATMEL Corporation – SPI Serial EEPROM

3.4 AC Characteristics (Continued)
Applicable over recommended operating range from T_AI = –40°C to +85°C, V_CC = As Specified,
CL = 1 TTL Gate and 30pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
t_LZ
HOLD to Output Low Z
4.5–5.5
0
25
2.5–5.5
0
50
1.8–5.5
0
100
4.5–5.5
40
t_HZ
HOLD to Output High Z
2.5–5.5
80
1.8–5.5
200
4.5–5.5
40
t_DIS
Output Disable Time
2.5–5.5
80
1.8–5.5
200
4.5–5.5
5
t_WC
Write Cycle Time
2.5–5.5
5
1.8–5.5
5
Endurance⁽¹⁾ 3.3V, 25°C, Page Mode
1M
Note: 1. This parameter is characterized and is not 100% tested.
Units
ns
ns
ns
ms
Write Cycles
4. Serial Interface Description
Master: The device that generates the serial clock.
Slave: Because the Serial Clock pin (SCK) is always an input, the AT25320B/640B always operates as a slave.
Transmitter/receiver: The AT25320B/640B has separate pins designated for data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
Serial Opcode: After the device is selected with CS going low, the first byte will be received. This byte contains the
opcode that defines the operations to be performed.
Invalid Opcode: If an invalid opcode is received, no data will be shifted into the AT25320B/640B, and the Serial Output
pin (SO) will remain in a high-impedance state until the falling edge of CS is detected again. This will reinitialize the serial
communication.
Chip Select: The AT25320B/640B is selected when the CS pin is low. When the device is not selected, data will not be
accepted via the SI pin, and the Serial Output pin (SO) will remain in a high-impedance state.
Hold: The HOLD pin is used in conjunction with the CS pin to pause the AT25320B/640B. When the device is selected
and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial
communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the
SI pin will be ignored while the SO pin is in the high-impedance state.
Write Protect: The Write Protect pin (WP) will allow normal read/write operations when held high. When the WP pin is
brought low and WPEN bit is one, all write operations to the status register are inhibited. WP going low while CS is still
low will interrupt a Write to the status register. If the internal write cycle has already been initiated, WP going low will have
no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status
register is zero. This will allow the user to install the AT25320B/640B in a system with the WP pin tied to ground and still
be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to one.
Atmel AT25320B/640B [DATASHEET]
6
8535G–SEEPROM–11/2012