AT18F040_14 Datasheet, PDF (6/16 Pages) ATMEL Corporation – Very Low-cost Configuration Memory

6. Pin Description
Table 6-1. Pin Descriptions
Name
DATA
CLK
RESET/OE
CE
CF
CEO
TMS
TCK
TDI
TDO
VCCINT
NC
VCCO
GND
VCCJ
Type
I/O
I
I
I
I
O
I
I
I
O
I
-
Power Supply
Ground
Power Supply
20-lead TSSOP
1
3
8
10
7
13
5
6
4
17
18
2, 9, 12, 14, 15, 16
19
11
20
6.1 DATA (D0)
Open-collector bi-directional data pin. This pin has an internal 20 KΩ pull-up resistor.
6.2 CLK
Clock input. Used to increment the internal address and bit counter for reading and program-
ming. This pin has an internal 20 KΩ pull-up resistor.
6.3 RESET/OE
Output Enable (active High) and RESET (active Low). A Low level on RESET/OE resets both
the address and bit counters. A High level (with CE Low) enables the data output driver. This pin
has an internal 20 KΩ pull-up resistor.
6.4 CE
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address
counter and enables the data output driver. A High level on CE disables both the address and bit
counters and forces the device into a low-power standby mode. This pin has an internal 20 KΩ
pull-up resistor.
6.5 CF
Configuration Pulse (open-drain output). Allows JTAG CONFIG instruction to initiate FPGA con-
figuration without powering down the FPGA. This is an open-drain output that is pulsed Low by
the JTAG CONFIG command.
6 AT18F010/002/040/080 [Preliminary]
3672A–CNFG–1/08