ATA5423_06 Datasheet, PDF (58/100 Pages) ATMEL Corporation – UHF ASK/FSK Transceiver

Figure 9-6. Timing Diagram for Failed Bit Check (Condition CV_Lim < Lim_min)
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
Bit check
Demod_Out
Bit check failed (CV_Lim < Lim_min)
1/2 Bit
Bit-check counter
0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112
T_{Startup_Sig_Proc}
T_Bit-check
Start-up mode
Bit-check mode
0
T_Sleep
Sleep mode
Figure 9-7. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
Bit check
Demod_Out
Bit check failed (CV_Lim ≥ Lim_min)
1/2 Bit
Bit-check counter
0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112131415161718192021222324
T_{Startup_Sig_Proc}
T_Bit-check
Start-up mode
Bit-check mode
0
T_Sleep
Sleep mode
9.1.6
Duration of the Bit Check
If no transmitter is present during the bit check, the output of the ASK/FSK demodulator delivers
random signals. The bit check is a statistical process and T_Bit-check varies for each check. There-
fore, an average value for T_Bit-check is given in the electrical characteristics. T_Bit-check depends on
the selected bit-rate range and on T_XDCLK. A higher bit-rate range causes a lower value for
T_Bit-check, resulting in a lower current consumption in RX polling mode.
58 ATA5423/25/28/29
4841C–WIRE–05/06