AT89C51CC01 Datasheet, PDF (58/170 Pages) ATMEL Corporation – Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory

Registers
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the master must send an address FFh. To communicate with slaves A
and B, but not slave C, the master can send and address FBh.
Table 35. SCON Register
SCON (S:98h)
Serial Control Register
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
7
6
5
4
3
2
1
0
Bit
Mnemonic Description
Framing Error bit (SMOD0=1)
FE
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SM0
Serial port Mode bit 0 (SMOD0=0)
Refer to SM1 for serial port mode selection.
SM1
Serial port Mode bit 1
SM0 SM1 Mode
0
0 Shift Register
0
1 8-bit UART
1
0 9-bit UART
1
1 9-bit UART
Baud Rate
F_XTAL/12 (or F_XTAL /6 in mode X2)
Variable
F_XTAL/64 or F_XTAL/32
Variable
SM2
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3.
REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3
TB8 Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
RB8
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
Transmit Interrupt flag
TI
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other
modes.
Receive Interrupt flag
RI
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 29. and
Figure 30. in the other modes.
Reset Value = 0000 0000b
Bit addressable
58 A/T89C51CC01
4129L–CAN–08/05