AT32UC3A3256S_14 Datasheet, PDF (57/94 Pages) ATMEL Corporation – High Performance, Low Power 32-bit Atmel AVR Microcontroller

AT32UC3A3
7.11 EBI Timings
7.11.1
SMC Signals
These timings are given for worst case process, T = 85⋅C, VDDIO = 3V and 40 pF load
capacitance.
Table 7-30. SMC Clock Signal
Symbol
Parameter
Max.⁽¹⁾
1/(t_CPSMC)
SMC Controller Clock Frequency
1/(t_cpcpu)
Note: 1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB.
Unit
MHz
Table 7-31. SMC Read Signals with Hold Settings
Symbol
Parameter
Min.
Unit
NRD Controlled (READ_MODE = 1)
SMC₁
SMC₂
SMC₃
SMC₄
SMC₅
SMC₇
SMC₈
SMC₉
Data Setup before NRD High
12
ns
Data Hold after NRD High
0
ns
NRD High to NBS0/A0 Change⁽¹⁾
NRD High to NBS1 Change⁽¹⁾
NRD High to NBS2/A1 Change⁽¹⁾
NRD High to A2 - A23 Change⁽¹⁾
NRD High to NCS Inactive⁽¹⁾
nrd hold length * t_CPSMC - 1.3
ns
nrd hold length * t_CPSMC - 1.3
ns
nrd hold length * t_CPSMC - 1.3
ns
nrd hold length * t_CPSMC - 1.3
ns
(nrd hold length - ncs rd hold length) * t_CPSMC - 2.3
ns
NRD Pulse Width
nrd pulse length * t_CPSMC - 1.4
ns
NRD Controlled (READ_MODE = 0)
SMC₁₀
Data Setup before NCS High
11.5
ns
SMC₁₁
Data Hold after NCS High
0
ns
SMC₁₂
NCS High to NBS0/A0 Change⁽¹⁾
ncs rd hold length * t_CPSMC - 2.3
ns
SMC₁₃
NCS High to NBS0/A0 Change⁽¹⁾
ncs rd hold length * t_CPSMC - 2.3
ns
SMC₁₄
NCS High to NBS2/A1 Change⁽¹⁾
ncs rd hold length * t_CPSMC - 2.3
ns
SMC₁₆
NCS High to A2 - A23 Change⁽¹⁾
ncs rd hold length * t_CPSMC - 4
ns
SMC₁₇
NCS High to NRD Inactive⁽¹⁾
ncs rd hold length - nrd hold length)* t_CPSMC - 1.3
ns
SMC₁₈
NCS Pulse Width
ncs rd pulse length * t_CPSMC - 3.6
ns
Note: 1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”.
57
32072SH–AVR32–10/2012