ATMEGA64RFR2_14 Datasheet, PDF (533/611 Pages) ATMEL Corporation – Microcontroller with Low Power

ATmega256/128/64RFR2
31.10.11 Flash Data Byte Register
The Flash Data Byte Register provides an efficient way to load the entire Flash page
buffer before executing Page Write, or to read out/verify the content of the Flash. A
state machine sets up the control signals to the Flash and senses the strobe signals
from the Flash, thus only the data words need to be shifted in/out.
The Flash Data Byte Register actually consists of the 8-bit scan chain and an 8-bit
temporary register. During page load, the Update-DR state copies the content of the
scan chain over to the temporary register and initiates a write sequence that within 11
TCK cycles loads the content of the temporary register into the Flash page buffer. The
AVR automatically alternates between writing the low and the high byte for each new
Update-DR state, starting with the low byte for the first Update-DR encountered after
entering the PROG_PAGELOAD command. The Program Counter is pre-incremented
before writing the low byte, except for the first written byte. This ensures that the first
data is written to the address set up by PROG_COMMANDS, and loading the last
location in the page buffer does not make the Program Counter increment into the next
page.
During Page Read, the content of the selected Flash byte is captured into the Flash
Data Byte Register during the Capture-DR state. The AVR automatically alternates
between reading the low and the high byte for each new Capture-DR state, starting with
the low byte for the first Capture-DR encountered after entering the
PROG_PAGEREAD command. The Program Counter is post-incremented after reading
each high byte, including the first read byte. This ensures that the first data is captured
from the first address set up by PROG_COMMANDS, and reading the last location in
the page makes the program counter increment into the next page.
Figure 31-20. Flash Data Byte Register
STROBES
State
Machine
TDI
ADDRESS
Flash
EEPROM
Fuses
Lock Bits
D
A
T
A
TDO
The state machine controlling the Flash Data Byte Register is clocked by TCK. During
normal operation in which eight bits are shifted for each Flash byte, the clock cycles
needed to navigate through the TAP-controller automatically feeds the state machine
for the Flash Data Byte Register with sufficient number of clock pulses to complete its
operation transparently for the user. However, if too few bits are shifted between each
Update-DR state during page load, the TAP-controller should stay in the Run-Test/Idle
state for some TCK cycles to ensure that there are at least 11 TCK cycles between
each Update-DR state.
8393C-MCU Wireless-09/14
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