U2794B Datasheet, PDF (5/15 Pages) TEMIC Semiconductors – 1000 MHz Quadrature Demodulator

U2794B
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified); V_S = 5 V, T_amb = 25°C, referred to test circuit
System impedance Z_O = 50 W, fiLO = 950 MHz, PiLO = -10 dBm
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
3.2
“Power DOWN”
4
LO Input, LO_in
4.1
Frequency range
4.2
Input level
4.3
Input impedance
4.4
Voltage standing
wave ratio
(2)
See Figure 12
See Figure 5
14
V_POFF
17
f_iLO
70
17
P_iLO
-12
-10
17
Z_iLO
50
17
VSWR_LO
1.2
4.5
Duty-cycle range
5
RF Input, RF_in
5.1
Noise figure (DSB)
at 950 MHz ⁽³⁾
symmetrical output at 100 MHz
17
DCR_LO
0.4
7, 8
NF
12
10
Max.
1
Unit Type*
V
D
1000 MHz
D
-5
dBm
D
W
D
2
D
0.6
D
dB
D
5.2
Frequency range
f_iRF = Fi_LO ± BW_YQ
7, 8
f_iRF
40
1030 MHz
D
5.3
-1 dB input
compression point
High gain
Low gain
5.4
Second order IIP
(4)
7, 8
7, 8
P_1dBHG
P_1dBLG
IIP_2HG
-8
dBm
D
+3.5
35
dBm
D
5.5
Third order IIP
High gain
Low gain
7, 8
IIP_3HG
IIP_3LG
+3
dBm
D
+13
5.6
LO leakage
Symmetric input
7, 8
L_OL
Asymmetric input
£ -60
£ -55
dBm
D
5.7
Input impedance
see Figure 12
7, 8
Z_iRF
6
I/Q Outputs (I, IX, Q, QX) Emitter Follower I = 0.6 mA
500II0.8
WIIpF
D
6.1
3–dB bandwidth
w/o external C
1, 2, 19,
BWI/Q
³ 30
20
MHz
D
6.2
I/Q amplitude error
1, 2, 19,
Ae
20
-0.5
£ ±0.2 +0.5
dB
B
6.3
I/Q phase error
1, 2, 19,
Pe
20
-3
£ ±1.5
+3
Deg
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. During power-down status a load circuitry with DC-isolation to GND is assumed, otherwise a current of I » (VS -0.8 V)/RI
has to be added to the above power-down current for each output I, IX, Q, QX.
2. The required LO-Level is a function of the LO frequency (see Figure 8).
3. Measured with input matching. For 950 MHz, the optional transmission line T3 at the RF input may be used for this pur-
pose. Noise figure measurements without using the differential output signal result in a worse noise figure.
4. Using Pins 7 and 8 as a symmetric RF input, the second-order IIP can be improved.
5. Due to test board parasitics, this bandwidth may be reduced and not be equal for I, IX, Q, QX. If symmetry and full band-
width is required, the lowpass Pins 3, 4 and 9, 10 should be isolated from the board. the bandwidth of the I/Q outputs can
be increased further by using a resistor between Pins 3, 4, 9 and 10. These resistors shunt the internal loads of
RI ~ 5.4 kW. The decrease in gain here has to be considered.
6. The internal current of the output emitter followers is 0.6 mA. This reduces the undistorted output voltage swing at a 50 W
load to approsimately 30 mV. For low signal distortion the load impedance should be RI ³ 5 kW.
7. Referred to the level of the output vector I² + Q²
8. The low-gain status is achieved with an open or high-ohmic Pin 11. A recommended application circuit for switching
between high and low gain status is hown in Figure 3.
5
4653C–CELL–06/03