TH7815ACC Datasheet, PDF (5/9 Pages) ATMEL Corporation – 50 MHz 4096 Linear CCDs

TH7815ACC
The following diagram shows the detailed timing for the pixel readout:
Figure 3. Pixel Readout Timing Diagram
Φ ^L1
Tpixel
90%
tr
10%
Φ ^L2
≥ ^{0 ns}
90%
tf
10%
±
50%
Φ^R
≥10 ns
Duty cycle: 50% ± 10%
Crossover at 50% ± 10%
Rise and fall time ≤ 10 ns
Rise and fall time ≤ 8 ns
floating diode level
Offset in darkness
VIDEO OUTPUTS
Reset Feedthrough
Video signal
Video outputs are synchronous
Video signal occurs on ΦL2 falling edge
First useful pixel occurs on 5th
falling edge of ΦL2 after ΦP
Exposure Time
Reduction
Antiblooming Gate
High Level
Low Level
Pulse Min.
The TH7815ACC antiblooming structure provides an electronic shutter capability by
clocking phase ΦA during the line period. The timing diagram is described below:
ΦA
Min.
Typ.
8.5
9
2
4
200 ns
Max.
9.5
7
Unit Clock Capacitance < 200 pF
V
Low Level Sets Saturation Level
V
See Pixel Saturation Adjustment
5
1995A–IMAGE–04/02