AT91RM3400_05 Datasheet, PDF (5/8 Pages) ATMEL Corporation – ARM7TDMI®-based Microcontroller

6058B–ATARM–08/04
AT91RM3400 Errata Sheet
12. SSC: RXSYN and TXSYN not cleared when read
The status bits RXSYN and TXSYN are active during a complete serial clock period
and are not immediately cleared when SSC_SR is read.
Problem Fix/Workaround
The user must enable the interrupt relevant to RXSYN and TXSYN.
11. SSC: Receiver Speed Limitations
If RF is programmed as an input, the maximum clock frequency is MCK divided by
2.
If RF is programmed as an output and RK is programmed as an input, the maximum
clock frequency is MCK divided by 6.
If RF and RK are both programmed as outputs, the maximum clock frequency is
MCK divided by 4.
Problem Fix/Workaround
None
10. SSC: Transmitter Speed Limitations
If both TF and TK are programmed as outputs, the maximum clock frequency is
MCK divided by 4.
If TF is programmed as an output and TK is programmed as an input, the maximum
clock frequency is MCK divided by 8.
If both TF and TK are programmed as inputs, the maximum clock frequency is MCK
divided by 8.
If TF is programmed as an input and TK is programmed as an output, the maximum
clock frequency is MCK divided by 4.
Problem Fix/Workaround
None
9. SSC: Disabling the SSC does not stop the Frame Synchronization signal
generation.
Generating RF can be stopped only by programming the FSOS field in SSC_RFMR
to 0x0.
Generating TF can be stopped only by programming the FSOS field in SSC_TFMR
to 0x0.
Problem Fix/Workaround
None
8. SSC: No delay when start condition overlays data transmit.
When transmission of data is programmed at the end of a frame and the start condi-
tion of the following frame is detected at the end of the current frame, the delay
programmed by the STTDLY bit (in the SSC_RCMR and in the SSC_TCMR regis-
ters) is not performed on the next frame. Transmission starts immediately
regardless of the programming of the field STTDLY.
Problem Fix/Workaround
None
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