AT25DF321A Datasheet, PDF (5/58 Pages) ATMEL Corporation – 32-Megabit 2.7-volt Minimum SPI Serial Flash Memory

3. Block Diagram
Figure 3-1. Block Diagram
CS
SCK
SI (SIO)
SO (SOI)
WP
HOLD
INTERFACE
CONTROL
AND
LOGIC
AT25DF321A [Preliminary]
CONTROL AND
PROTECTION LOGIC
Y-DECODER
X-DECODER
I/O BUFFERS
AND LATCHES
SRAM
DATA BUFFER
Y-GATING
FLASH
MEMORY
ARRAY
4. Memory Array
To provide the greatest flexibility, the memory array of the AT25DF321A can be erased in four
levels of granularity including a full chip erase. In addition, the array has been divided into phys-
ical sectors of uniform size, of which each sector can be individually protected from program and
erase operations. The size of the physical sectors is optimized for both code and data storage
applications, allowing both code and data segments to reside in their own isolated regions. The
Memory Architecture Diagram illustrates the breakdown of each erase level as well as the
breakdown of each physical sector.
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3686C–DFLASH–12/08