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AT24C08_14 Datasheet, PDF (5/19 Pages) ATMEL Corporation – Schmitt Trigger, Filtered Inputs for Noise Suppression
AT24C01A/02/04/08/16
Table 5. AC Characteristics
Applicable over recommended operating range from TA = −40°C to +125°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
AT24C01A/02/04/08,
2.7V
AT24C16, 2.7V
AT24C01A/02/04/08/16,
5.0V
Symbol Parameter
Min
Max
Min
Max
Min
fSCL
Clock Frequency, SCL
400(1)
400
tLOW
Clock Pulse Width Low
1.2
1.2
1.2
tHIGH
tI
Clock Pulse Width High
Noise Suppression Time(2)
0.6
0.6
0.6
50
50
tAA
Clock Low to Data Out Valid
0.1
0.9
0.1
0.9
0.1
tBUF
Time the bus must be free before
a new transmission can start(3)
1.2
1.2
1.2
Max
Units
400
kHz
µs
µs
50
ns
0.9
µs
µs
tHD.STA
Start Hold Time
0.6
0.6
0.6
µs
tSU.STA
Start Set-up Time
0.6
0.6
0.6
µs
tHD.DAT
Data In Hold Time
0
0
0
µs
tSU.DAT
tR
tF
Data In Set-up Time
Inputs Rise Time(3)
Inputs Fall Time(3)
100
100
100
300
300
300
300
ns
300
ns
300
ns
tSU.STO
Stop Set-up Time
0.6
0.6
0.6
µs
tDH
Data Out Hold Time
50
50
50
ns
tWR
Write Cycle Time
5
5
5
ms
Endurance 5.0V, 25°C
1M
1M
1M
Write
Cycles
Notes:
1. The AT24C01A/02/04/08 bearing the process letter “D” on the package (the mark is located in the lower right corner on the
topside of the package), guarantees 400 kHz (2.5V, 2.7V).
2. This parameter is characterized and is not 100% tested (TA = 25°C).
3. This parameter is characterized and is not 100% tested.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
5
3256F–SEEPR–10/04