AT24C08A_14 Datasheet, PDF (5/20 Pages) ATMEL Corporation – Low-voltage and Standard-voltage Operation

AT24C01A/02/04/08A/16A
Table 5. AC Characteristics
Applicable over recommended operating range from T_A = 40C to +125C, V_CC = +2.7V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
AT24C01A/02/04/08A/16A
Symbol
Parameter
Min
Max
Units
f_SCL
t_LOW
t_HIGH
t_I
t_AA
t_BUF
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time⁽¹⁾
Clock Low to Data Out Valid
Time the bus must be free before
a new transmission can start⁽²⁾
400
kHz
1.2
µs
0.6
µs
50
ns
0.1
0.9
µs
1.2
µs
t_HD.STA
t_SU.STA
t_HD.DAT
t_SU.DAT
t_R
t_F
t_SU.STO
t_DH
t_WR
Endurance⁽²⁾
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time⁽²⁾
Inputs Fall Time⁽²⁾
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25C, Page Mode
0.6
µs
0.6
µs
0
µs
100
ns
300
ns
300
ns
0.6
µs
50
ns
5
ms
1M
Write Cycles
Note: 1. This parameter is characterized and is not 100% tested (T_A = 25C).
2. This parameter is characterized.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see to
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see to Figure 5 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has received
each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode
which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the
completion of any internal operations.
5
5092D–SEEPR–4/07