AT83SND2CMP3_0605 Datasheet, PDF (49/97 Pages) ATMEL Corporation – Single-Chip MP3 Decoder with Full Audio Interface

USB Interrupt System
Interrupt System Priorities
Figure 35. USB Interrupt Control System
AT83SND2CMP3
D+
USB
D-
Controller
EUSB
EA
IE1.6
IE0.7
Interrupt Enable
00
01
10
11
IPH/L
Priority Enable
Lowest Priority Interrupts
Table 1. Priority Levels
IPHUSB
0
0
1
1
IPLUSB
0
1
0
1
USB Priority Level
0..................Lowest
1
2
3..................Highest
USB Interrupt Control System
As shown in Figure 36, many events can produce a USB interrupt:
• TXCMPL: Transmitted In Data. This bit is set by hardware when the Host accept a
In packet.
• RXOUTB0: Received Out Data Bank 0. This bit is set by hardware when an Out
packet is accepted by the endpoint and stored in bank 0.
• RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints). This bit is set
by hardware when an Out packet is accepted by the endpoint and stored in bank 1.
• RXSETUP: Received Setup. This bit is set by hardware when an SETUP packet is
accepted by the endpoint.
• STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints). This bit is set
by hardware when a STALL handshake has been sent as requested by STALLRQ,
and is reset by hardware when a SETUP packet is received.
• SOFINT: Start of Frame Interrupt . This bit is set by hardware when a USB start of
frame packet has been received.
• WUPCPU: Wake-Up CPU Interrupt. This bit is set by hardware when a USB resume
is detected on the USB bus, after a SUSPEND state.
• SPINT: Suspend Interrupt. This bit is set by hardware when a USB suspend is
detected on the USB bus.
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