AT80251G2D_14 Datasheet, PDF (47/77 Pages) ATMEL Corporation – Compare and Conditional Jump Instructions

AT/TSC8x251G2D
Table 40. Bus Cycles AC Timings; V_DD = 2.7 to 5.5 V, T_A = -40 to 85°C
12 MHz
16 MHz
Symbol Parameter
Min Max Min Max Unit
T_OSC 1/F_OSC
83
62
ns
T_LHLL ALE Pulse Width
72
52
ns⁽²⁾
T_AVLL Address Valid to ALE Low
71
51
ns⁽²⁾
T_LLAX Address hold after ALE Low
T_RLRH(1) RD#/PSEN# Pulse Width
T_WLWH WR# Pulse Width
14
6
ns
163
121
ns⁽³⁾
165
124
ns⁽³⁾
T_LLRL(1) ALE Low to RD#/PSEN# Low
17
11
ns
T_LHAX ALE High to Address Hold
T_RLDV(1) RD#/PSEN# Low to Valid Data
T_RHDX(1) Data Hold After RD#/PSEN# High
90
57
ns⁽²⁾
133
92
ns⁽³⁾
0
0
ns
T_RHAX(1) Address Hold After RD#/PSEN# High
0
0
ns
T_RLAZ(1) RD#/PSEN# Low to Address Float
0
0
ns
T_RHDZ1 Instruction Float After RD#/PSEN# High
59
48
ns
T_RHDZ2 Data Float After RD#/PSEN# High
225
175
ns
T_RHLH1 RD#/PSEN# high to ALE High (Instruction)
60
47
ns
T_RHLH2 RD#/PSEN# high to ALE High (Data)
226
172
ns
T_WHLH WR# High to ALE High
T_AVDV1 Address (P0) Valid to Valid Data In
T_AVDV2 Address (P2) Valid to Valid Data In
T_AVDV3 Address (P0) Valid to Valid Instruction In
226
172
ns
289
160 ns⁽²⁾⁽³⁾
296
211 ns⁽²⁾⁽³⁾
144
98
ns⁽³⁾
T_AXDX Data Hold after Address Hold
0
0
ns
T_AVRL(1) Address Valid to RD# Low
T_AVWL1 Address (P0) Valid to WR# Low
T_AVWL2 Address (P2) Valid to WR# Low
111
64
111
64
158
116
ns⁽²⁾
ns⁽²⁾
ns⁽²⁾
T_WHQX Data Hold after WR# High
82
66
ns
T_QVWH Data Valid to WR# High
135
103
ns⁽³⁾
T_WHAX WR# High to Address Hold
168
125
ns
Notes: 1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2·T_OSC.
3. If wait states are added by extending RD#/PSEN#/WR#, add 2N·T_OSC (N = 1..3).
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4135F–8051–11/06