AT697F_14 Datasheet, PDF (45/176 Pages) ATMEL Corporation – SPARC V8 High Performance Low-power 32-bit Architecture

SDCLK
A
IOS*
OE*
BRDY*
D
CB
Figure 25. Asynchronous BRDY*-Controlled IO Read Access (MCFG1.abrdy=1)
lead-in
read
n ws
brdy
data
lead-out
Address
Address
Address
1.5 SDCLK min.
Data
Chkbits
Figure 26. Synchronous BRDY*-Controlled SRAM4 Read Access (MCFG1.abrdy=0)
read
n ws
brdy
data
SDCLK
A
Address
Address
Address
RAMS*[4]
RAMOE*[4]
BRDY*
D
Data
CB
Chkbits
Figure 27. Asynchronous BRDY*-Controlled SRAM4 Read Access (MCFG1.abrdy=1)
read
n ws
brdy
data
SDCLK
A
Address
Address
Address
RAMS*[4]
RAMOE*[4]
BRDY*
1.5 SDCLK
D
Data
CB
Chkbits
45 AT697F
7703E–AERO–08/11