ATAM862-4_06 Datasheet, PDF (44/110 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

This timer starts running automatically after any power-on reset! If the watchdog function is not
activated, the timer can be restarted by writing into the T1C1 register with T1RM = 1.
Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The watchdog
timer is a 3-bit counter that is supplied by a separate output of Timer 1. It generates a system
reset when the 3-bit counter overflows. To avoid this, the 3-bit counter must be reset before it
overflows. The application software has to accomplish this by reading the CWD register.
After power-on reset the watchdog must be activated by software in the $RESET initialization
routine. There are two watchdog modes, in one mode the watchdog can be switched on and off
by software, in the other mode the watchdog is active and locked. This mode can only be
stopped by carrying out a system reset.
The watchdog timer operation mode and the time interval for the watchdog reset can be pro-
grammed via the watchdog control register (WDC).
Figure 22-7. Timer 1 Module
SYSCL
SUBCL
CL1
MUX
Prescaler
14 bit
WDCL
Watchdog ^NRST
4 bit
T1CS
T1MUX
T1BP
T1IM
INT2
T1OUT
Figure 22-8. Timer 1 and Watchdog
T1C1 T1RM T1C2 T1C1 T1C0
Write of the
T1C1 register
3
Decoder
MUX for interval timer
RES ^{Q1 Q2 Q3 Q4 Q5}
Q8
Q11
CL1
CL
Q6
Q8
Q11
Decoder
2
WDC WDL WDR WDT1 WDT0
MUX for watchdog timer
RES
Watchdog
mode control
T1C2 T1BP T1IM
T1MUX
T1IM=0
INT2
Q14 _SUBCL
T1IM=1
T1OUT
Q14
Watchdog
Divider / 8
WDCL
Divider
RESET
RESET
(NRST)
Read of the
CWD register
44 ATAM862-4
4551F–4BMCU–05/06