AT90LS4433_14 Datasheet, PDF (44/126 Pages) ATMEL Corporation – Data and Non-volatile Program Memory

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
time-out periods are shown inTable 16.
Table 16. Watchdog Timer Prescale Select⁽¹⁾
Number of WDT
WDP2 WDP1 WDP0 Oscillator Cycles
0
0
0
16K cycles
0
0
1
32K cycles
0
1
0
64K cycles
0
1
1
128K cycles
1
0
0
256K cycles
1
0
1
512K cycles
1
1
0
1,024K cycles
1
1
1
2,048K cycles
Typical Time-out
at V_CC = 3.0V
47 ms
94 ms
0.19 s
0.38 s
0.75 s
1.5 s
3.0 s
6.0 s
Typical Time-out
at V_CC = 5.0V
15 ms
30 ms
60 ms
0.12 s
0.24 s
0.49 s
0.97 s
1.9 s
Note:
1. The frequency of the Watchdog Oscillator is voltage dependent, as shown in the
Electrical Characteristics section.
The WDR (Watchdog Reset) instruction should always be executed before the
Watchdog Timer is enabled. This ensures that the reset period will be in accordance
with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without
reset, the Watchdog Timer may not start counting from zero.
To avoid unintentional MCU reset, the Watchdog Timer should be disabled or Reset
before changing the Watchdog Timer Prescale Select.
44 AT90S/LS4433
1042H–AVR–04/03