AT90LS2343_14 Datasheet, PDF (44/64 Pages) ATMEL Corporation – AVR – High-performance and Low-power RISC Architecture

Data Polling EEPROM
Data Polling Flash
7. At the end of the programming session, RESET can be set high to commence
normal operation.
8. Power-off sequence (if needed):
Set CLOCK/XTAL1 to “0”.
Set RESET to “1”.
Turn V_CC power off.
When a byte is being programmed into the EEPROM, reading the address location
being programmed will give the value P1 until the auto-erase is finished, and then the
value P2 will be given. See Table 18 for P1 and P2 values.
At the time the device is ready for a new EEPROM byte, the programmed value will read
correctly. This is used to determine when the next byte can be written. This will not work
for the values P1 and P2, so when programming these values, the user will have to wait
for at least the prescribed time t_{WD_PROG} before programming the next byte. See Table 22
for t_{WD_PROG} value. As a chip-erased device contains $FF in all locations, programming
of addresses that are meant to contain $FF can be skipped. This does not apply if the
EEPROM is reprogrammed without first chip-erasing the device.
Table 18. Read Back Value during EEPROM Polling
Part
P1
P2
AT90S2323
$00
$FF
AT90S2343
$00
$FF
When a byte is being programmed into the Flash, reading the address location being
programmed will give the value $FF. At the time the device is ready for a new byte, the
programmed value will read correctly. This is used to determine when the next byte can
be written. This will not work for the value $FF, so when programming this value, the
user will have to wait for at least t_{WD_PROG} before programming the next byte. As a chip-
erased device contains $FF in all locations, programming of addresses that are meant
to contain $FF can be skipped.
Figure 36. Low-voltage Serial Downloading Waveforms
SERIAL DATA INPUT
MSB
LSB
PB0(MOSI)
SERIAL DATA OUTPUT
MSB
LSB
PB1(MISO)
SERIAL CLOCK INPUT
PB2(SCK)
44 AT90S/LS2323/2343
1004D–09/01