ATAR862-4_07 Datasheet, PDF (43/112 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

22.7 Timer 1
Figure 22-6. UTCM Block Diagram
SYSCL
SUBCL
from clock module
Timer 1
MUX
Watchdog
Interval / Prescaler
T1OUT
Timer 3
Capture 3
Control
T3I
8-bit Counter 3
Demodu-
lator 3
MUX
Compare 3/1
Modu-
lator 3
Compare 3/2
TOG3
MUX
Timer 2
4-bit Counter 2/1
Compare 2/1
Modu-
lator 2
Control
POUT
T2I
8-bit Counter 2/2
MUX DCG
Compare 2/2
TOG2
MUX
SSI
Receive buffer
8-bit shift register
Transmit buffer
SCL
Control
ATAR862-4
NRST
INT2
T3O
INT5
T2O
I/O bus
INT4
SC
SD
INT3
The Timer 1 is an interval timer which can be used to generate periodical interrupts and as pres-
caler for Timer 2, Timer 3, the serial interface and the watchdog function.
The Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL or
SYSCL. The timer output signal can be used as prescaler clock or as SUBCL and as source for
the Timer 1 interrupt. Because of other system requirements, the Timer 1 output T1OUT is syn-
chronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and
OSC-Stop -> yes), the output T1OUT is stopped (T1OUT = 0). Nevertheless, the Timer 1 can be
active in SLEEP and generate Timer 1 interrupts. The interrupt is maskable via the T1IM bit and
the SUBCL can be bypassed via the T1BP bit of the T1C2 register. The time interval for the
timer output can be programmed via the Timer 1 control register T1C1.
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4552H–4BMCU–07/07