ATAM893-D Datasheet, PDF (43/98 Pages) ATMEL Corporation – Flash Version for ATAR080, ATAR090/890 and ATAR092/892

5.3.2.5
Timer 2 Control Register (T2C)
Bit 3
Bit 2
Bit 1
Bit 0
T2C
T2CS1 T2CS0 T2TS
T2R
ATAM893-D
Address: '7'hex — Subaddress: '0'hex
Reset value: 0000b
T2CS1
T2CS0
T2TS
T2R
Timer 2 Clock Select bit 1
Timer 2 Clock Select bit 0
Timer 2 Toggle with Start
T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start
T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with T2R
Timer 2 Run
T2R = 0, Timer 2 stop and reset
T2R = 1, Timer 2 run
5.3.2.6
Table 5-8. Timer 2 Clock Select Bits
T2CS1
0
0
1
1
T2CS0
0
1
0
1
Input Clock (CL 2/1) of Counter Stage 2/1
System clock (SYSCL)
Output signal of Timer 1 (T1OUT)
Internal shift clock of SSI (SCL)
Output signal of Timer 3 (TOG3)
Timer 2 Mode Register 1 (T2M1)
T2M1
Bit 3
T2D1
Bit 2
T2D0
Bit 1
T2MS1
Bit 0
T2MS0
Address: '7'hex — Subaddress: '1'hex
Reset value: 1111b
T2D1
T2D0
T2MS1
T2MS0
Timer 2 Duty cycle bit 1
Timer 2 Duty cycle bit 0
Timer 2 Mode Select bit 1
Timer 2 Mode Select bit 0
Table 5-9.
T2D1
1
1
0
0
Timer 2 Duty Cycle Bits
T2D0
1
0
1
0
Function of Duty Cycle Generator (DCG)
Bypassed (DCGO0)
Duty cycle 1/1 (DCGO1)
Duty cycle 1/2 (DCGO2)
Duty cycle 1/3 (DCG03)
Additional Divider Effect
/1
/2
/3
/4
43
4680C–4BMCU–01/05