ATA5823 Datasheet, PDF (43/98 Pages) ATMEL Corporation – UHF ASK/FSK Transceiver

ATA5823/ATA5824
Table 12-25. Control Register 8 (Function of Bit 4, Bit 3, Bit 2, Bit 1, Bit 0)
PWSET4
2⁴
0
PWSET3
2³
0
PWSET2
2²
0
PWSET1
2¹
0
PWSET0
2⁰
0
Function (TX Mode, FD Mode)
(SETPWR: Programmable internal
resistor to reduce the output power
in FD and TX mode)
PWSET
SETPWR = 800Ω + (31 – PWSET)
× 3 kΩ (typically)
0
0
0
0
0
1
1
.
.
.
.
.
16 (default)
1
0
0
0
0
SETPWR = 800Ω + (31 – 16) ×
3 kΩ (typically)
.
.
.
.
.
1
1
1
1
0
30
1
1
1
1
1
31
Normally the SETPWR resistor at pin 19 is used in full-duplex mode to decrease the output
power until the level at RF_IN is low enough for reception of signals (PWSELECT = 0). With
PWSELECT = 1 this resistor can also be used in normal half-duplex TX operation to adjust the
output power for production tolerances.
12.3.9
Status Register (ADR 16)
The status register indicates the current status of the transceiver and is readable via the 4-wire
serial interface. Setting Power_On or an event on N_Power_On is indicated by an IRQ.
Reading the status register resets the bits Power_On, DVCC_RST and the IRQ.
Table 12-26. Status Register
Status Bit Function
N_Power_On
Power_On
DVCC_RST
Status of pin N_PWR_On
Pin N_PWR_ON = 0 → N_Power_On = 1
Pin N_PWR_ON = 1 → N_Power_On = 0
(Figure 12-3 on page 45)
Indicates that the transceiver was woken up by pin PWR_ON (rising edge on
pin PWR_ON). During Power_On = 1, the bit CLK_ON in control register 3 is
set to 1 (Figure 12-4 on page 46).
DVCC_RST is set to 1 if the supply voltage of the RAM (V_DVCC) was too low and the
information in the RAM may be lost.
DVCC_RST = 0 → supply voltage of the RAM ok
DVCC_RST = 1 → supply voltage of the RAM was too low (typically V_DVCC < 1.6V)
If the transceiver changes from OFF mode to IDLE mode, DVCC_RST will be set to 1.
Reading the Status register resets DVCC_RST to 0.
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4829C–RKE–09/05