ATTINY10_14 Datasheet, PDF (41/170 Pages) ATMEL Corporation – Atmel 8-bit AVR Microcontroller

10.2
Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of
one I/O-port pin, here generically called Pxn.
Figure 10-2. General Digital I/O⁽¹⁾
REx
QD
PUExn
Q _CLR
RESET
QD
DDxn
Q _CLR
RESET
WEx
WDx
RDx
1
Pxn
QD
PORTxn
0
Q _CLR
SLEEP
RESET
WRx
WPx
RRx
SYNCHRONIZER
DQ
LQ
DQ
PINxn
Q
SLEEP:
clk _I/O:
SLEEP CONTROL
I/O CLOCK
WEx:
REx:
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
RPx
clk _I/O
WRITE PUEx
READ PUEx
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
Note: 1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O, and SLEEP
are common to all ports.
10.2.1 Configuring the Pin
Each port pin consists of four register bits: DDxn, PORTxn, PUExn, and PINxn. As shown in “Register Description”
on page 50, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, the
PUExn bits at the PUEx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured
as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
ATtiny4/5/9/10 [DATASHEET] 41
8127F–AVR–02/2013