ATAR090_14 Datasheet, PDF (41/75 Pages) ATMEL Corporation – Up to 6 External/Internal Interrupt Sources

ATAR090/ATAR890
Synchronous Serial Interface
(SSI)
SSI Features
• 2- and 3-wire NRZ
• 2-wire mode, additional internal 2-wire link for multi-chip packaging solutions
• With Timer 2
– Bi-phase modulation
– Manchester modulation
– Pulse-width demodulation
– Burst modulation
SSI Peripheral Configuration
The synchronous serial interface (SSI) can be used either for serial communication with
external devices such as EEPROMs, shift registers, display drivers, other microcontrol-
lers, or as a means for generating and capturing on-chip serial streams of data. External
data communication takes place via Port 4 (BP4),a multi-functional port which can be
software configured by writing the appropriate control word into the P4CR register. The
SSI can be configured in any of the following ways:
1. 2-wire external interface for bi-directional data communication with one data ter-
minal and one shift clock. The SSI uses Port BP43 as a bi-directional serial data
line (SD) and BP40 as a shift clock line (SC).
2. 3-wire external interface for simultaneous input and output of serial data, with a
serial input data terminal (SI), a serial output data terminal (SO) and a shift clock
(SC). The SSI uses BP40 as a shift clock (SC), while the serial data input (SI) is
applied to BP43 (configured in P4CR as input). Serial output data (SO) in this
case is passed through to BP42 (configured in P4CR to T2O) via Timer 2 output
stage (T2M2 configured in mode 6).
3. Timer/SSI combined modes – the SSI used together with Timer 2 is capable of
performing a variety of data modulation and demodulation functions (see section
“Timer”). The modulating data is converted by the SSI into a continuous serial
stream of data which is in turn modulated in one of the timer functional blocks.
4. Multi-chip link (MCL) – the SSI can also be used as an interchip data interface for
use in single package multi-chip modules or hybrids. For such applications, the
SSI is provided with two dedicated pads (MCL_SD and MCL_SC) which act as a
two-wire chip-to-chip link. The MCL can be activated by the MCL control bit.
Should these MCL pads be used by the SSI, the standard SD and SC pins are
not required and the corresponding Port 4 ports are available as conventional
data ports.
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