AT32AP7000_09 Datasheet, PDF (41/63 Pages) ATMEL Corporation – AVR32 32-bit Microcontroller

AT32AP7000
8. Boot Sequence
This chapter summarizes the boot sequence of the AT32AP7000. The behaviour after power-up
is controlled by the Power Manager.
8.1 Starting of clocks
After power-up, the device will be held in a reset state by the Power-On Reset (POR) circuitry
until the voltage has reached the power-on reset rising threshold value (see Electrical Character-
istics for details). This ensures that all critical parts of the device are properly reset.
Once the power-on reset is complete, the device will use the XIN0 pin as clock source. XIN0 can
be connected either to an external clock, or a crystal. The OSCEN_N pin is connected either to
VDD or GND to inform the Power Manager on how the XIN0 pin is connected. If XIN0 receives a
signal from a crystal, dedicated circuitry in the Power Manager keeps the part in a reset state
until the oscillator connected to XIN0 has settled. If XIN0 receives an external clock, no such set-
tling delay is applied.
On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have
a divided frequency, all parts of the system recieves a clock with the same frequency as the
XIN0 clock.
Note that the power-on reset will release reset at a lower voltage threshold than the minimum
specified operating voltage. If the voltage is not guaranteed to be stable by the time the device
starts executing, an external brown-out reset circuit should be used.
8.2 Fetching of initial instructions
After reset has been released, the AVR32AP CPU starts fetching instructions from the reset
address, which is 0xA000_0000. This address lies in the P2 segment, which is non-translated,
non-cacheable, and permanently mapped to the physical address range 0x0000_0000 to
0x2000_0000. This means that the instruction being fetched from virtual address 0xA000_0000
is being fetched from physical address 0x0000_0000. Physical address 0x0000_0000 is
mapped to EBI SRAM CS0. This is the external memory the device boots from.
The code read from the SRAM CS0 memory is free to configure the system to use for example
the PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the
clocks to unused peripherals.
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