AT49F008A Datasheet, PDF (4/18 Pages) ATMEL Corporation – 8-megabit (1M x 8/512K x 16) Flash Memory

RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high-impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read or
standby mode, depending upon the state of the control inputs. By applying a 12V ± 0.5V input
signal to the RESET pin, the boot block array can be reprogrammed even if the boot block pro-
gram lockout feature has been enabled (see Boot Block Programming Lockout Override
section).
ERASURE: Before a byte or word can be reprogrammed, it must be erased. The erased state
of memory bits is a logic “1”. The entire device can be erased by using the Chip Erase com-
mand or individual sectors can be erased by using the Sector Erase command.
CHIP ERASE: The entire device can be erased at one time by using the 6-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is t_EC.
If the boot block lockout has been enabled, the chip erase will not erase the data in the boot
block; it will erase the main memory block and the parameter blocks only. After the chip erase,
the device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into four sec-
tors that can be individually erased. There are two 4K word parameter block sections, one
boot block, and the main memory array block. The Sector Erase command is a six-bus cycle
operation. The sector address is latched on the falling WE edge of the sixth cycle while the
30H data input command is latched at the rising edge of WE. The sector erase starts after the
rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will auto-
matically time to completion. Whenever the main memory block is erased and reprogrammed,
the two parameter blocks should be erased and reprogrammed before the main memory block
is erased again. Whenever a parameter block is erased and reprogrammed, the other param-
eter block should be erased and reprogrammed before the first parameter block is erased
again. Whenever the boot block is erased and reprogrammed, the main memory block and the
parameter blocks should be erased and reprogrammed before the boot block is erased again.
BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logic
“0”) on a byte-by-byte or word-by-word basis. Programming is accomplished via the internal
device command register and is a four-bus cycle operation. The device will automatically gen-
erate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified t_BP cycle
time. The Data Polling feature may also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has
a programming lockout feature. This feature prevents programming of data in the designated
block once the feature has been enabled. The size of the block is 8K words. This block,
referred to as the boot block, can contain secure code that is used to bring up the system.
Enabling the lockout feature will allow the boot code to stay in the device while data in the rest
of the device is updated. This feature does not have to be activated; the boot block’s usage as
a write-protected region is optional to the user. The address range of the boot block is 00000H
to 03FFFH for the AT49F008A; FC000H to FFFFFH for the AT49F008AT; 00000H to 01FFFH
for the AT49F8192A; and 7E000H to 7FFFFH for the AT49F8192AT.
4 AT49F008A(T)/8192A(T)
1199G–FLASH–11/02